The average scalar (=integer) instructions per cycle is pretty comparable between Pentium III and Xtensa LX6, the original ESP32 CPU representing the worst case.
While P3 is superscalar, it could only execute about 0.9 instructions per cycle on average. Of course you can optimize for it and get better results in certain cases.
Most Xtensa scalar instructions take just 1 clock, branches 3 for taken, 1 for not taken. So 0.7-0.8 instructions per clock is a reasonable estimate. Assuming of course code is executing from SRAM.
Xtensa's FPU is slow, and it lacks divide and square root instructions. Clock for clock, P3 probably outperforms it by 3-4x. It also lacks 64-bit floats.
While P3 is superscalar, it could only execute about 0.9 instructions per cycle on average. Of course you can optimize for it and get better results in certain cases.
Most Xtensa scalar instructions take just 1 clock, branches 3 for taken, 1 for not taken. So 0.7-0.8 instructions per clock is a reasonable estimate. Assuming of course code is executing from SRAM.
Xtensa's FPU is slow, and it lacks divide and square root instructions. Clock for clock, P3 probably outperforms it by 3-4x. It also lacks 64-bit floats.