points by ranger_danger 2 hours ago | 0 comments
Cute but wouldn't work with ssize_t :)
VHDL's array/vector syntax actually works a similar way:
-- gives 0, 1, 2, 3:
for i in 0 to 3 loop
-- gives 3, 2, 1, 0:
for i in 3 downto 0 loop
-- Source - https://stackoverflow.com/a/7642026 -- Posted by Kerrek SB -- Retrieved 2026-10-29, License - CC BY-SA 3.0
[–] fourthark 2 hours ago
[–] ranger_danger 1 hour ago
For me it does not work because I'd want to use it with values < 0, but the for loop checks for > 0, so I would have to modify that first.